1. Field of Invention
The present invention relates to semiconductor memory and in particular to an array structure using split gate transistor cells and providing ways to avoid reverse-tunnel-disturb and punch through-disturb as well as a method to re-write cells that are feed forward disturbed.
2. Description of Related Art
Applications such as data memory or smart card require a byte alterable memory. These applications are cost sensitive and require that the byte alterable capability be implemented at a minimum cost. In order to keep a byte alterable memory compact, an array architecture is required that provides a compact memory and eliminates any resulting disturb conditions. Creating a byte alterable memory, in general, requires segmentation of word lines and source lines, which in turn adds to the amount of semiconductor real estate required to implement the byte alterable memory.
U.S. Pat. No. 6,376,876 B1 (Shin et al.) is directed to a NAND type flash memory array that uses a low resistance common source line with low aspect ratio bit line contact holes. In U.S. Pat. No. 6,400,603 B1 (Blyth et al.) a flash EEPROM array is directed to the reduced size of blocks or pages that are to be erased in a write or an erase operation. U.S. Pat. No. 6,128,220 (Banyai et al.) is directed to a flash memory device that provides a byte-alterable nonvolatile memory. U.S. Pat. No. 6,121,087 (Mann et al.) is directed to an integrated circuit device with an embedded EEPROM memory. U.S. Pat. No. 6,088,269 (Lambertson) is directed to a compact page erasable EEPROM without the use of the control gate to improve electron tunneling efficiency during programming. U.S. Pat. No. 5,812,452 (Hoang) is directed to a byte selectable and byte alterable memory array. U.S. Pat. No. 5,544,103 (Lambertson) is directed to a compact, electrically erasable and programmable nonvolatile memory device which has unique programming and erasing techniques in which the control gate is eliminated as a means for improving electron tunneling efficiency. In U.S. Pat. No. 5,033,023 an EEPROM is directed to a byte erase operation.
In an array using floating gate transistors connected by a common source line between adjacent rows and a common bit line connected between cells in a column, a program disturb is possible for erased cells. The program disturb can be either a punch-through disturb or a reverse-tunnel-disturb. The punch-through disturb can occur in an erased cell that shares a common source line and bit line with a cell being programmed. The punch-through disturb will cause the disturbed cell, which has been erased, to be weakly programmed since there is non-zero channel current. The non-zero channel current will change the disturbed cell from an erased state (logical “1”) to a programmed state (logical “0”) after several iterations. The reverse-tunnel-disturb can occur in unselected erased cells within a page during programming, but located on the adjacent row of a selected page. The voltage on the common source line is couple by capacitance to the floating gate of the unselected cell. If a defect exists in the oxide separating the floating gate and the control gate, Fowler-Nordheim tunneling can occur, which could program the unselected cell.
Referring to FIG. 1 of prior art, if cell C1 is programmed then cell C2 can suffer punch-through disturb (common source line and common bit line). Cell C4 can suffer reverse tunneling disturb (common source line but not common bit line) when cell C1 is programmed, and cell C3 can suffer feed forward (FF) disturb (common source line and common word line)